The present invention relates to apparatus for decoding a plurality of instructions simultaneously and executing the decoded plurality of instructions simultaneously in a variable word length instruction format.
A parallel processing operation is generally performed in a conventional data processing apparatus in order to increase the rate of data processing. For example, in processing two instructions in a parallel manner, two decoders are provided to decode two instructions simultaneously and to operate two execution units simultaneously. In Japanese Patent Publication JP-A-63-49843, a first and a second decoder decodes two (arithmetic and logical operation) instructions, respectively, to operate an arithmetic operation unit and a logical operation unit simultaneously to improve the system performance. In this example, the instructions are decoded in a parallel manner in the fixed word length instruction format, so that it is easy to realize such decoding.
In a variable word length instruction format in which the length of the instruction code changes depending on the kind of operations and the addressing mode, the position of an instruction subsequent to the instruction which is being decoded is determined by the result of the decoding of the present instruction, so that it is difficult to decode a plurality of instructions simultaneously. In order to cope with this situation, a plurality of second decodes which decode simultaneously instruction words subsequent to the instructions which are being decoded are provided, or a selector which selects an instruction word input to the second instruction decoder is provided and controlled in accordance with the result of the decoding by the first instruction decoder to determine the input to the second instruction decoder. Therefore, the number of decoders would increase and the time required for decoding would increase undesirably.
There is a data processing apparatus in which since it is difficult to decode a plurality of instructions simultaneously in a variable word length instruction format the results of decoding the respective instructions are beforehand stored, such results for two instructions are given simultaneously to an execution unit to simultaneously execute the two instructions in a parallel manner. ("Study of CPU Architecture of 32-Bit Microprocessor TX3 Based on TRON Specifications", TECHNICAL REPORT OF COMPUTER SYSTEMS, Institute of Electronics, Information and Communication Engineers (IEICE), Vol. 87, No. 422, 1988.)
According to the data processing apparatus of this apparatus, a predetermined quantity of the results of decoding instructions is stored in a decoded-instruction buffer, and the results of the decoding are supplied to a plurality of execution units so long as the decoded results in the decoded-instruction buffer can be used repeatedly via a program loop. In order to store the decoded results and improve the effect of reuse of the decoded result, a decoded instruction buffer of a large capacity is required. For the first use of the loop, namely, until storage of the decoded result in the decoded-instruction buffer is completed, the transmission ability of the decoded instruction buffer is limited to the throughput of one-instruction decoding.